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AN1709/1003 1/38 1.0 AN1709 application note emc design guide for st microcontrollers by cyril troise - microcontroller division applications introduction the continuing demand for more performance, complexity and cost reduction require the sem- iconductor industry to develop microcontrollers with both high density design technology and higher clock frequencies. this has intrinsically increased the noise emission and noise sensi- tivity. application developers therefore, must now apply emc hardening techniques in the design of firmware, pcb layout and at system level. this note aims to explain st microcon- troller emc features and compliance standards to help application designers reach the op- timum level of emc performance. 1
2/38 table of contents 38 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 emc definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 emc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 ems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 emi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 emc characterization of st microcontrollers . . . . . . . . . . . . . . . . . . 5 2.1 electromagnetic susceptibility (ems) . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 functional ems test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1.1 functional electrostatic discharge test (f_esd test) . . . . . . . . . 5 2.1.1.2 fast transient burst (ftb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1.3 st severity level & behavior class . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 latch-up (lu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2.1.2.1 static latch-up (lu) test: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2.2 dynamic latch-up (dlu) test: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.3 absolute electrical sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.3.1 human body model test sequence . . . . . . . . . . . . . . . . . . . . . . 12 2.1.3.2 machine model test sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 emi radiated test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 2.2.2 emi level classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 st mcu design strategy & emc specific feature . . . . . . . . . . . . . . . . . . 17 3.1 susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.3 i/o features & properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.3.1 electrostatic discharge and latch-up . . . . . . . . . . . . . . . . . . . . . 21 3.1.3.2 protective interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.3.3 internal circuitry: digital i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.3.4 internal circuitry: analog input pin . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.4 multiple vdd & vss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 internal pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2 global low power approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2.1 low powered oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2.2 internal voltage regulators (for mcus with low power core). . . . 29
3/38 table of contents 3.2.3 output i/o current limitation & edge timing control . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 emc guidelines for mcu based applications . . . . . . . . . . . . . . . . . . . . . 30 4.1 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 handling precautions for esd protection. . . . . . . . . . . . . . . . . . . 34 4.3 firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4 web links to emc related organisations . . . . . . . . . . . . . . . . . . . . 36 5 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4/38 emc design guide for st microcontrollers 1 emc definitions 1.1 emc electromagnetic compatibility (emc) is the capability of a system to work properly, undis- turbed by the electromagnetic phenomena present in its normal environment, and not to create electrical disturbances that would interfere with other equipment. 1.2 ems the electromagnetic susceptibility (ems) level of a device is the resistance to electrical dis- turbances and conducted electrical noise. electrostatic discharge (esd) and fast transient burst (ftb) tests determine the reliability level of a device operating in an undesirable electro- magnetic environment. 1.3 emi the electromagnetic interference (emi) is the level of conducted or radiated electrical noise sourced by the equipment. conducted emission propagates along a cable or any interconnec- tion line. radiated emission propagates through free space. 2
5/38 emc design guide for st microcontrollers 2 emc characterization of st microcontrollers 2.1 electromagnetic susceptibility (ems) two different type of tests are performed: n tests with device power-supplied (functional ems tests & latch-up): the device behaviour is monitored during the stress. n one test with device not powered supplied (absolute electrical sensitivity): the device functionality and integrity is checked on tester after stress. 2.1.1 functional ems test functional tests are performed to measure the robustness of st microcontrollers running in an application. based on a simple program (toggling 2 leds through i/o ports), the product is stressed by 2 different emc events until a run-away condition (failure) occurs. 2.1.1.1 functional electrostatic discharge test (f_esd test) this test is performed on any new microcontroller devices.each pin is tested individually with a single positive or negative electrical discharge.this allows failures investigations inside the chip and further application recommendations to protect the concerned microcontroller sensi- tive pins against esd. high static voltage has both natural and man made origins. some specific equipment can re- produce this phenomenon in order to test the device under real conditions. equipment, test sequence and standards are described here below. st microcontroller f_esd qualification test uses standards given in table 1 as reference. table 1. esd standards aec-q100-reue is the automotive controlling document. f_esd tests uses a signal source and a power amplifier to generate a high level field into the microcontroller. the insulator is using a conical tip. this tip is placed on the device or equip- ment under test (dut or eut) and an electrostatic discharge is applied (see figure 1. ). european norm international norm description en 61000-4-2 iec 1000-4-2 conducted esd test
6/38 emc design guide for st microcontrollers figure 1. esd test equipment the equipment used to perform f_esd test is a generator nsg 435 (schaffner) com- pliant with the norm iec 1000-4-2. the discharges are directly applied on each pin of the mcu. figure 2. typical esd current waveform in contact-mode discharge esd generator ground plane insulation mains connections eut (en 61000-4-2) time current 100% 90% i(30ns) i(60ns) 10% 30ns 60ns t r =0.7 to 1.0 ns
7/38 emc design guide for st microcontrollers figure 3. simplified diagram of the esd generator (rch = 50m w ; rd = 330 w ) 2.1.1.2 fast transient burst (ftb) more complex than functional esd, this test which submits the device to a large quantity of emitted disturbances in a short time, is useful for detecting infrequent and unrecoverable (class b or c) microcontroller states. ftb disturbances (see figure 4. ) are applied to the mi- crocontroller power lines through a capacitive coupling network. st microcontroller ftb test correlates with the standards given in table 2 table 2. ftb standards figure 4. ftb waveform diagram the spike frequency is 5 khz. the generator produces bursts of spikes that last 15 ms every 300 ms (75 spikes). the fast transients are coupled to the device dut with capacitors c c (see figure 5. ). european norm international norm description en61000-4-4 iec 1000-4-4 fast transient burst esd generator rch rd discharge tip hv relay cs = 150 pf discharge return connection bur s t vol tag e burst voltage voltage pulse burst length 15ms burst period 300ms time time time 0.9vpk vpk 0.5vpk 0.1vpk 5ns 50ns repetition frequency: 5khz; bursts will be repeated for at least 1 minute. rising and duration time (30%) are re- ferred to a 50 w load
8/38 emc design guide for st microcontrollers figure 5. coupling network measurements are performed on a ground plane. the generator is connected to ground plane by a short wire. the supply wires are 10 cm from the ground plane. the dut is on the insu- lator 10 cm from the ground plane. the ftb voltage level is increased until the device failure. severity levels and class help application designers to determine which st microcontrollers are suitable for their target application, based on the susceptibility level (severity level) and type of behavior (class) indicated in the datasheet. 2.1.1.3 st severity level & behavior class the 1000-4-2 and 1000-4-4 standards do not refer specifically to semiconductor components such as microcontrollers. usually electromagnetic stress is applied on other parts of the system such as connectors, mains, supplies... the energy level of the f_esd and ftb test decreases before reaching the microcontroller, governed by the laws of physics. a large amount of statistical data collected by st on the behaviour of mcus in various application en- vironments has been used to develop a correlation chart between st f_esd or ftb test voltage and 1000-4-2/1000-4-4 severity levels (see table 3 ). table 3. st esd severity levels in addition to this severity level, mcu behaviour under esd stress can be grouped into dif- ferent behaviour classes (see table 4 ) according to en 50082-2 norm: severity level esd (1000-4-2) equipment standard (kv) ftb (1000-4-4) equipment standard (kv) st testing voltage st internal emc test (kv) 120.50-0.5 2410.5-1 3621-1.5 484>1.5 to the device power supply under test cc +v dd gnd nsg 2025 gnd cc +v dd l
9/38 emc design guide for st microcontrollers table 4. st behavior classes any st microcontroller under the acceptance limits is rejected as a fail. the target level is the level used by st to define good ems performance. class b could be caused by: C a parasitic reset correctly managed by the firmware (preferable case). C deprogramming of a peripheral register or memory recovered by the application. C a blocked status, recovered by a watchdog or other firmware implementation. class c could be caused by: C deprogramming of a peripheral register or memory not recovered by the application. C a blocked application status requiring an external user action. table 5 shows st target and acceptance limits. table 5. f_esd / ftb target level & acceptance limit between acceptance limit and target level, the device is relatively susceptible to noise. special care during system design should be taken to avoid susceptibility issues. table 6 shows how f_esd / ftb test results are presented in st datasheets. table 6. example of f_esd / ftb test results class a class b class c class d no failure detected failure detected but self recovery after distur- bance needs an external user action to recover normal functionality normal functionality cannot be recovered acceptance limit target level f_esd 0.5kv >1kv ftb 0.5kv >1.5kv symbol ratings conditions severity/criteria v f_esd voltage limits to be applied on any i/o pin to induce a functional disturbance t a = +25c 2/a, 3/b v ftb fast transient voltage burst limits to be applied through 100pf on vss and vdd pins to induce a functional distur- bance t a = +25c 3/b
10/38 emc design guide for st microcontrollers 2.1.2 latch-up (lu) 2.1.2.1 static latch-up (lu) test: the latch-up is a phenomenon which is defined by a high current consumption resulting from an overstress that triggers a parasitic thyristor structure and need a disconnection of the power supply to recover the initial state. notes 1 the overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or any other abnormal condition that causes the parasitic thyristor structure to be- come self-sustaining. 2 latch-up will not damage the device if the current through the low-impedance path is suffi- ciently limited in magnitude or duration. this test conforms to the eia/jesd 78 ic latch-up standard. true lu is self-sustaining and once triggered, the high current condition will remain until the power supply voltage is removed from the device. a temporary lu condition is considered to have been induced if the high current condition stops when only the trigger voltage is re- moved. two complementary static tests are required on 10 parts to assess the latch-up performance: n power supply overvoltage (applied to each power supply pin) simulates a user induced situation where a transient over-voltage is applied on the power supply. n current injection (applied to each input, output and configurable i/o pin) simulates an application induced situation where the applied voltage to a pin is greater than the maximum rated conditions, such as severe overshoot above v dd or undershoot below ground on an input due to ringing. table 7 shows how lu test result is presented in st datasheets. table 7. example of the lu test result on st72f521 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2.1.2.2 dynamic latch-up (dlu) test: the product is evaluated for its lu susceptibility to esd discharges when the microcontroller is running. symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c, t a = +125c (de- pending on the temperature range of the device) a
11/38 emc design guide for st microcontrollers increasing electrostatic discharges are supplied to every pin of the component until a latch-up occurs. result is the maximum tolerated voltage without latch-up. dlu test methodology and characterization: electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the microcontroller is running to as- sess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the microcontroller and the com- ponent is put in reset mode. table 8 shows how the dlu test result is presented in st datasheets. table 8. example of dlu test result on st72f521 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). lu/dlu test equipment is same as the one used for the functional ems (see figure 1. ). 2.1.3 absolute electrical sensitivity this test is performed to assess the components immunity against destruction caused by esd. any devices that fails this electrical test program is classified as a failure. using automatic esd tester, electro-static discharges (a positive then a negative pulse sep- arated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1): n= supply pins). two models are usually simulated: human body model (hbm) and machine model (mm). all parts are re-tested on the production tester to verify the static and dynamic parame- ters still comply with the device datasheet (see figure 6. ). this test conforms to the jesd22-a114a/a115a standard. see figure 6. and the following test sequences. symbol parameter conditions class 1) dlu dynamic latch-up class v dd = 5v f osc = 4mhz, t a = +25c a
12/38 emc design guide for st microcontrollers figure 6. absolute electrical sensitivity test models 2.1.3.1 human body model test sequence the hbm esd pulse simulates the direct transfer of electrostatic charge, from the human body, to a test device. a 100pf capacitor is discharged through a switching component and a 1.5 kohm series resistor. this is currently the most requested industry model, for classifying device sensitivity to esd. C c l is loaded through s1 by the hv pulse generator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the c occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the c is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. 2.1.3.2 machine model test sequence the mm esd pulse emulates the rapid direct transfer of electrostatic charge, from a charged conductive object, such as a metallic tool or fixture, to a test device. this model consists of a discharged 200pf capacitor, with no series resistor. the demand for mm esd testing has in- creased, with the replacement of individual packaging by automated systems. C c l is loaded through s1 by the hv pulse generator. C s1 switches position from generator to the c. C a discharge from c l to the c occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the c is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. r (machine resistance), in series with s2, ensures a slow discharge of the c. table 9 shows how hbm/mm esd test results are presented in st datasheets. c s2 r=1500w s1 high voltage c l =100pf pulse generator c s2 high voltage c l =200pf pulse generator r=10k~10mw s1 human body model machine model
13/38 emc design guide for st microcontrollers table 9. example of hbm/mm esd test results on st72f521 notes: 1. data based on characterization results, not tested in production. 2.2 electromagnetic interference (emi) 2.2.1 emi radiated test this test correlates with the sae j1752/3 standard. this test gives a good evaluation of the contribution of the microcontroller to radiated noise in an application environment. it takes into account the mcu chip and also the package which has a major influence on the noise radiated by the device. below is the package emi contribution from the highest to the lowest: sdip/dip sop qfp tqfp the test is performed in a transverse electromagnetic mode cell (temcell) which allows radiated noise measurement in two directions, rotating the test board by 90 test description: the firmware running is based on a simple application, toggling 2 leds through the i/o ports. the main directives for an sae pcb are ( figure 8. ): C 100 x 100mm square board C at least 2-layer board (ideally 4-layer). C 5mm conductive edges on both sides connected to ground for contact with temcell. figure 7. shows a typical example of an mcu emc test board schematics. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 200
14/38 emc design guide for st microcontrollers figure 7. example of test board schematics for st7 220 220 led 1 led 2 10k bp1 pb2 pb3 pb1 xtal 1 xtal 2 vdda vdd1 vdd2 vdd3 +5v 100 nf vssa vss1 vss2 vss3 reset vpp gnd 4.7k bp2 gnd 10k gnd
15/38 emc design guide for st microcontrollers figure 8. test printed circuit board specification according j1752/3 sae standard
16/38 emc design guide for st microcontrollers 2.2.2 emi level classification the emi classifications are directly based on the absolute frequency and amplitude of the emitted noise. several international norms exist, based on different measurement methodolo- gies, or emission levels, but the classification principle remains the same. the standardized diagram (see figure 9. ) is useful to get a synthesis and a classification of emi results, according to a standard framework. each st microcontroller emi result is classi- fied according to 4 sae levels. figure 9. emi level classification: below is the potential risk associated with each emi level: _ higher than 4 . high risk due to emi level. _ level 4 . may require cost for emi compliance. _ level 3 . moderate emi risk. _ level 2 . minimal emi risk. table 10 shows how emi test results are presented in st datasheets. table 10. example of emi results for st72f521 to give a synthetic view of the emission spectrum, the highest emission level of 3 ranges of frequency is indicated. emi data are provided with relevant information such as the device package and cpu frequency. dbu v 60 40 30 20 10 0 -20 0.1 1 10 30 100 1000 mhz level 4 level 3 level 2 level 1
17/38 emc design guide for st microcontrollers 3 st mcu design strategy & emc specific feature at the initial specification of a new product, emc dedicated features are implemented after an identification of emc constraints imposed by the mcu target applications. you should refer to the specific product datasheet to know which of these feature described here are embedded. figure 10. overview of specific features embedded in st microcontrollers 3.1 susceptibility 3.1.1 low voltage detector (lvd) the purpose of the lvd is to ensure that the microcontroller will always work in its safe oper- ating area (see figure 12. ). in terms of ems, the presence of the lvd makes the mcu more robust, ensuring that if any outside disturbance affects the power supply, the application can recover safely. when v dd is below the ? min working v dd ? the behaviour of the microcontroller is no longer guaranteed. there is not enough power to decode/execute the instructions and/or read the memory. when v dd is below the lvd level the microcontroller enters in reset state (internal reset high) in order to prevent unpredictable behaviour. there are 2 levels with 250mv hys- teresis in order to avoid oscillating when the micro restarts. when a lvd reset occurs, a bit is set by hw. this bit can be used to recover an application. the low voltage detector function generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power- down keeping the microcontroller in reset. st microcontrollers for emc in low power oscillator i/o protection watchdog lvd/avd internal pll internal voltage regulators (for mcus with low power core) multi oscillator embedded features controlled slope (firmware management refer to an 1015)
18/38 emc design guide for st microcontrollers the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv it+ when v dd is rising Cv it- when v dd is falling the lvd function is illustrated in figure 11. . the voltage threshold can be configured by option byte to be low, medium or high. provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it- , the mcu can only be in two modes: C under full software control C in static safe reset in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes : the lvd allows the device to be used without any external reset circuitry. the lvd is an optional function which can be selected by option byte. refer to product spec- ification. figure 11. low voltage detector vs reset v dd v it+ reset v it- v hys
19/38 emc design guide for st microcontrollers figure 12. max. operating frequency vs. supply voltage. the minimum value of each supply range is limited by the lvd threshold which can be config- ured at one of three levels (low, medium or high) depending on the application. 3.1.2 auxiliary voltage detector (avd) like the lvd, this feature improves ems performance by ensuring that the microcontroller be- haves safely when the power supply is disturbed by external noise. the avd feature can be used only if the lvd is activated . avd has also different levels (around 200mv above lvd levels), enabling a early warning before the reset caused by the lvd. then, when avd threshold is crossed, an interrupt is generated, requesting for example some user action or preparing the application to shut down in the interrupt routine until the power supply returns to the correct level for the device (refer to the product datasheet). example: if f cpu is between 8 mhz and 16 mhz the min. working level is 3.5 volt. the voltage detector function (avd) is based on an analog comparison between a v it- and v it+ reference value and the v dd main supply. the v it- reference value for falling voltage is lower than the v it+ reference value for rising voltage in order to avoid parasitic detection (hys- teresis). the output of the avd comparator is directly readable by the application software through a real time status bit (vdf). this bit is read only. the avd voltage threshold value is relative to the selected lvd threshold configured by op- tion byte (see microcontroller spec). vsupply freq. 8mhz 16mhz lvd high lvd med. lvd low absolute working window safe 16mhz area 3.8v reset issued safe 16mhz area. 3.5v reset safe 8mhz area issued
20/38 emc design guide for st microcontrollers if the avd interrupt is enabled, an interrupt is generated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcontroller. (see figure 13. ). the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay of the microcontroller), no avd interrupt will be generated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles then: C if the avd interrupt is enabled before the v it+(avd) threshold is reached, then 2 avd inter- rupts will be received: the first when the avdie bit is set, and the second when the threshold is reached. C if the avd interrupt is enabled after the v it+(avd) threshold is reached then only one avd interrupt will occur. figure 13. using the avd to monitor v dd v dd v it+(avd) v it-(avd) avdf bit 0 0 reset value if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 1 1 t rv voltage rise time
21/38 emc design guide for st microcontrollers 3.1.3 i/o feature s & properties although integrated circuit data sheets provide the user with conservative limits and condi- tions in order to prevent damage, sometimes it is useful for the hardware system designer to know the internal failure mechanisms: the risk of exposure to illegal voltages and conditions can be reduced by smart protection design. it is not possible to classify and to predict all the possible damage resulting from violating max- imum ratings and conditions, due to the large number of variables that come into play in de- fining the failures: in fact, when an overvoltage condition is applied, the effects on the device can vary significantly depending on lot-to-lot process variations, operating temperature, ex- ternal interfacing of the microcontroller with other devices, etc. in the following sections, background technical information is given in order to help system de- signers to reduce risk of damage to the microcontroller device. 3.1.3.1 electrostatic discharge and latch-up cmos integrated circuits are generally sensitive to exposure to high voltage static electricity, which can induce permanent damage to the device: a typical failure is the breakdown of thin oxides, which causes high leakage current and sometimes shorts. latch-up is another typical phenomenon occurring in integrated circuits: unwanted turning on of parasitic bipolar structures, or silicon-controlled rectifiers (scr), may overheat and rapidly destroy the device. these unintentional structures are composed of p and n regions which work as emitters, bases and collectors of parasitic bipolar transistors: the bulk resistance of the silicon in the wells and substrate act as resistors on the scr structure. applying voltages below v ss or above v dd , and when the level of current is able to generate a voltage drop across the scr parasitic resistor, the scr may be turned on; to turn off the scr it is neces- sary to remove the power supply from the device. st microcontroller design implements layout and process solutions to decrease the effects of electrostatic discharges (esd) and latch-up. of course it is not possible to test all devices, due to the destructive nature of the mechanism; in order to guarantee product reliability, destruc- tive tests are carried out on groups of devices, according to stmicroelectronics internal quality assurance standards and recommendations (see 2.1.2 latch-up (lu) ).
22/38 emc design guide for st microcontrollers 3.1.3.2 protective interface although st microcontroller input/output circuitry has been designed taking esd and latch- up problems into account, for those applications and systems where st microcontroller pins are exposed to illegal voltages and high current injections, the user is strongly recommended to implement hardware solutions which reduce the risk of damage: low-pass filters and clamp diodes are usually sufficient in preventing stress conditions. the risk of having out-of-range voltages and currents is greater for those signals coming from outside the system, where noise effect or uncontrolled spikes could occur with higher proba- bility than for the internal signals; it must be underlined that in some cases, adoption of filters or other dedicated interface circuitries might affect global microcontroller performance, in- ducing undesired timing delays, and impacting the global system speed. figure 14. digital input/output - push-pull pin output buffer p n p n n input buffer p esd protection circuitry port circuitry i/o circuitry p en en
23/38 emc design guide for st microcontrollers 3.1.3.3 internal circuitry: digital i/o pin figure 14. shows a schematic representation of an st microcontroller pin able to operate ei- ther as an input or as an output is shown. the circuitry implements a standard input buffer and a push-pull configuration for the output buffer. it is evident that although it is possible to disable the output buffer when the input section is used, the mos transistors of the buffer itself can still affect the behaviour of the pin when exposed to illegal conditions. in fact, the p-channel tran- sistor of the output buffer implements a direct diode to v dd (p-diffusion of the drain connected to the pin and n-well connected to v dd ), while the n-channel of the output buffer implements a diode to v ss (p-substrate connected to vss and n-diffusion of the drain connected to the pin). in parallel to these diodes, dedicated circuitry is implemented to protect the logic from esd events (mos, diodes and input series resistor). the most important characteristic of these extra devices is that they must not disturb normal operating modes, while acting during exposure to over limit conditions, avoiding permanent damage to the logic circuitry. according to the mcu used, some i/o pins can be programmed to work also as open-drain outputs, by simply writing in the corresponding register of the i/o port. the gate of the p- channel of the output buffer is disabled: it is important to highlight that physically the p-channel transistor is still present, so the diode to v dd works. in some applications it can occur that the voltage applied to the pin is higher than the v dd value (supposing the external line is kept high, while the microcontroller power supply is turned off): this condition w ill inject current through the diode, risking permanent damages to the device. in any case, programming i/o pins as open-drain can help when several pins in the system are tied to the same point: of course software must pay attention to program only one of them as output at any time, to avoid output driver contentions; it is advisable to configure these pins as output open-drain in order to reduce the risk of current contentions.
24/38 emc design guide for st microcontrollers figure 15. digital input/output - true open drain output in figure 15. a true open-drain pin schematic is shown. in this case all paths to v dd are re- moved (p-channel driver, esd protection diode, internal weak pull-up) in order to allow the system to turn off the power supply of the microcontroller and keep the voltage level at the pin high without injecting current in the device. this is a typical condition which can occur when several devices interface a serial bus: if one device is not involved in the communication, it can be disabled by turning off its power supply to reduce the system current consumption. when an illegal negative voltage level is applied to the microcontroller i/o pins (both versions, push-pull and true open-drain output) the clamp diode is always present and active (see esd protection circuitry and n-channel driver). pin output buffer n p n n input buffer esd protection circuitry port circuitry i/o circuitry p en en
25/38 emc design guide for st microcontrollers 3.1.3.4 internal circuitry: analog input pin figure 16. shows the internal circuitry used for analog input. it is primarily a digital i/o with an added analog multiplexer for the selection of the input channel of the analog to digital con- verter (adc). the presence of the multiplexer p-channel and n-channel can affect the behaviour of the pin when exposed to illegal voltage conditions. these transistors are controlled by a low noise logic, biased through av dd and av ss including p-channel n-well: it is important to always verify the input voltage value with respect to both analog power supply and digital power supply, in order to avoid unintentional current injections which (if not limited) could destroy the device. figure 16. digital input/output - push-pull output - analog multiplexer input pin output buffer p n p n n input buffer p e sd protection circuitry port circuitry i/o circuitry p en en n p p
26/38 emc design guide for st microcontrollers 3.1.4 multiple v dd & v ss . as already said for the i/o pins, in order to ensure st microcontroller compliance with respect to quality assurance recommendations concerning esd and latch-up, dedicated circuits are added to the different power supply and ground pins (digital and analog). these structures create preferred paths for the high current injected during discharges, avoiding damage to ac- tive logic and circuitry. it is important for the system designer to take this added circuitry into account, when applying different current levels and voltages to the power supply and ground pins. figure 17. shows schematically the protection net implemented on st microcontroller devices, composed of diodes and other special structures. the clamp structure between the v dd and v ss pins is designed to be active during very fast transitions (typical of electrostatic discharges). other paths are implemented through diodes: they limit the possibility of positively differentiating av dd and v dd (i.e. av dd > v dd ); similar considerations are valid for av ss and v ss due to the back-to-back diode structure imple- mented between the two pins. anyway, it must be highlighted that, because v ss and av ss are connected to the substrate of the silicon die (even though in different areas of the die itself), they represent the reference point from which all other voltages are measured, and it is rec- ommended to never differentiate av ss from v ss . note: if more than one pair of pins for v ss and v dd is available on the device, they are con- nected internally and the protection net diagram remains the same as shown in figure 17. . figure 17. power supply and ground configuration (on st9) n p p n v dd v ss av dd av ss v test
27/38 emc design guide for st microcontrollers 3.2 emission 3.2.1 internal pll some st microcontrollers have an embedded programmable pll clock generator allowing the usage of standard 3 to 5 mhz crystals to obtain a large range of internal frequencies (up to 24mhz). by these means, st microcontroller can operate with cheaper, medium frequency crystals, while still providing a high frequency internal clock for maximum system perform- ance. the high clock frequency source is contained inside the chip and does not go through the pcb (printed circuit board) tracks and external components. this reduces the potential noise emission of the application. the use of pll network also filters cpu clock against external sporadic disturbances (glitches). 3.2.2 global low power approach 3.2.2.1 low powered oscillator the oscillator is an major source of noise. to reduce this noise emission, the current driven by the oscillator is limited. the main clock of some of st microcontrollers can be generated by four different source types coming from the multi-oscillator block (mo). this allows the designer to easily select the best trade-off in terms of cost, performance and noise emission. the clock sources are listed below in order from the most noisy to the least noisy: n an external source n crystal or ceramic resonator oscillators n an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is se- lectable through the option byte. the associated hardware configurations are shown in table 11 . refer to the electrical characteristics section of the datasheet for more details in each case. external clock source in external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. crystal/ceramic oscillators this family of oscillators has the advantage of producing a very accurate rate on the main clock of the microcontroller. the selection within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to the microcon- troller datasheet for more details on the frequency ranges). in this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator
28/38 emc design guide for st microcontrollers pins in order to minimize output distortion and start-up stabilization time. the loading capaci- tance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid the delay needed for the the oscillator start-up. internal rc oscillator the internal rc oscillator is the most cost effective solution, with the drawback of lower fre- quency accuracy. its frequency is in the low single digit mhz range. in this mode, the two os- cillator pins have to be tied to ground. process variations will also bring some differences from lots to lots (20 to 60%). some st microcontrollers (refer to product specification) embed a process compensation. this feature is called trimmable internal rc. a procedure during test operation analyzes the process variation and calibrate the internal oscillator accordingly. this brings the internal rc accuracy to 1%. this procedure can be also performed by the user: refer to an1324 calibrating the rc oscillator of the st7flite0 using the mains table 11. st7 clock sources the st multi-oscillator system is designed for flexibility and to allow the system designer to find the best compromise between emission, accuracy and cost criteria. hardware configuration external clock external rc oscillator crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 st7 c ex r ex osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7
29/38 emc design guide for st microcontrollers 3.2.2.2 internal voltage regulators (for mcus with low power core). an internal voltage regulator is used to power some st microcontrollers cores starting from the external power supply. the voltage regulator reduces emi due to the mcu core with 2 effects: C lower cpu supply voltage C isolate cpu supply from external mcu supplies. 3.2.3 output i/o current limitation & edge timing control output buffers are embedded in st microcontrollers, their switching speed is controlled in order to avoid parasitic oscillations when they are switched. the mcu design makes a trade- off between noise and speed.
30/38 emc design guide for st microcontrollers 4 emc guidelines for mcu based applications the following guidelines result from experience gained in a wide variety of applications. 4.1 hardware the major noise receptors and generators are the tracks and wiring on the printed circuit board (pcb), especially those near the mcu. the first actions to prevent noise problems thus concern the pcb layout and the design of the power supply. in general, the smaller the number of components surrounding the mcu, the better the immu- nity versus noise. a romless solution, for instance, is typically more sensitive to and a bigger generator of noise than an embedded memory circuit. optimized pcb layout noise is basically received and transmitted through tracks and components which, once ex- cited, act as antennas. each loop and track includes parasitic inductance and capacitance which radiate and absorb energy once submitted to a variation of current, voltage or electro- magnetic flux. an mcu chip itself presents high immunity to and low generation of emi since its dimensions are small versus the wave lengths of emi signals (typically mm versus 10's of cm for emi sig- nals in the ghz range). so a single chip solution with small loops and short wires reduces noise problems. the initial action at the pcb level is to reduce the number of possible antennas. the loops and wires connected to the mcu such as supply, oscillator and i/o should be considered with a special attention. the oscillator loop has to be especially small since it operates at high fre- quency figure 18. a reduction of both the inductance and the capacitance of a track is generally difficult. prac- tical experience suggests that in most cases the inductance is the first parameter to be mini- mized.
31/38 emc design guide for st microcontrollers figure 18. pcb board oscillator layout examples the reduction of inductance can be obtained by making the lengths and surfaces of the track smaller. this can be obtained by placing the track loops closer on the same pcb layer or on top of one another ( figure 19. ). the resulting loop area is small and the electromagnetic fields reduce one another. the ratio in order of magnitude relating to the inductance value and the area defined by the wire loop is around 10nh/cm2. typical examples of low inductivity wires are coaxial, twisted pair cables or multiple layer pcbs with one ground and one supply layers. the current density in the track can also be smaller due to track enlargement or the paralleling of several small ca- pacitances mounted in the current flow. in critical cases, the distance between the mcu and the pcb, and therefore the surfaces of the loops between an mcu and its environment, has also to be minimized. this can be achieved by removing any socket between the mcu package and the pcb, by replacing a ce- ramic mcu package by a plastic one or by using surface mounting instead of dual in line packages. note: board vias are inductances. try to avoid them. if needed, use multi vias.
32/38 emc design guide for st microcontrollers figure 19. reduction of pcb tracks loop surfaces note: this test is done with a double sided pcb. insulator thickness is 1.5mm, copper thick- ness is 0.13mm. the overall board size is 65 x 200mm. power supply filtering the power supply is used by all parts of the circuit, so it has to be considered with special at- tention. the supply loops have to be decoupled to make sure that signal levels and power cur- rents do not interfere. these loops can be separated using star wiring with one node desig- nated as common for the circuit ( figure 20. ). the decoupling capacitance should be placed very close to the mcu supply pins to minimize the resultant loop. it should be also large enough to absorb, without significant voltage in- crease, parasitic currents coming from the mcu via the input protection diodes. the decou- pling of the board can be done with electrolytic capacitors (typ. 10f to 100f) since the die- lectric used in such capacitors provides a high volumic capacitance. however these capaci- tors behave like inductances at high frequency (typ. above 10mhz) while ceramic or plastic capacitors keep a capacitive behaviour at higher frequency. a ceramic capacitance of, for in- stance, 0.1f to 1f should be used as high frequency supply decoupling for critical chips op- erating at high frequency. high inductance low inductance
33/38 emc design guide for st microcontrollers figure 20. power supply lay-out examples i/o configuration an open (floating) pin is a potential hazard to the circuit. i/o pins which are not used in the application should be preferably configured in output low state. this will also minimize the current consumption. a m ajor source of emission in microcontroller based applications can be due to high speed digital i/o and communication interfaces such as spi, i2c clocks, usb or pwm... the rise/ fall times are critical. typical designs add rc low pass filters. shielding shielding can help in reducing noise sensitivity and emission, but its success depends directly on the material chosen as shield (high permeability, low resistivity) and on its connection to a stable voltage source including a decoupling capacitance via a low serial impedance (low in- ductance, low resistance). if the generator of major disturbances is near to the mcu board and can be identified as a strong dv/dt generator (i.e. a transformer or klystron), the noise is carried mainly by the elec- trostatic field. the critical coupling between the noise generator and the control board is ca- pacitive. a highly conductive shield (i.e. copper) creating a faraday cage around the control board may strongly increase the immunity.
34/38 emc design guide for st microcontrollers if the strongest source of perturbations is a di/dt generator (i.e. a relay), it is a high source of electromagnetic fields. therefore, the permeability of the shielding material (i.e. alloy) is cru- cial to increase the immunity of the board. in addition, the number and size of the holes on the shield should be reduced as much as possible to increase its efficiency. in critical cases, the implantation of a ground plane below the mcu and the removal of sockets between the device and the pcb can reduce the mcu noise sensitivity. indeed, both actions lead to a reduction of the apparent surface of loops between the mcu, its supply, its i/o and the pcb. 4.2 handling precautions for esd protection. electronic components have to be protected from the hazard of static electricity from the man- ufacturing stage down to where they are utilized in order to avoid esd related destruction. a specific no-compromise strategy is implemented at st for all esd sensitive products. from the wafer level to the shipping of finished goods, each workstation and processing step is guaranteed. for final packing, st uses anti-static tubes. this solution ensures full esd pro- tection of devices. however, the supplier's greatest efforts are in vain if the end user does not provide the same level of protection and care in the application. a relative humidity of 50% to 65% is the best to prevent electrostatic problems (the lower the relative humidity, the higher the electrostatic voltage). nevertheless, the person handling the semiconductors as well as the equipment will be charged to a certain level. the work environ- ment is very important to protect devices against static electricity anti-static electricity measures during work (1) conductive mat (2) wrist (3) conductive floor mat (4) work suit with anti-static measure (5) conductive shoes grounding the human body
35/38 emc design guide for st microcontrollers figure 21. grounding the human body (1) wrist ring (2) grounding wire: threaded copper wire, vinyl covered, about 1 meter (3) 250 kw to 1 mw resistance is built in device handling: static control wrist straps, used and connected properly, must be worn. all tools, persons, testing machines, which could come in contact with device leads, must be conductive and grounded. each tabletop must be protected with a conductive mat, properly grounded. use static control shoe strap. use vacuum pipes. storage box: keep parts in the original packing bags up to the very last moment of the production line. if bigger containers are used for in-plant transport of devices or pc boards, they must be elec- trically conductive like the carbon-loaded types. avoid use of high dielectric materials (like pol- ystyrene) for sub-assembly construction, storing, and transportation.
36/38 emc design guide for st microcontrollers equipment and tools: use ionized air blowers to neutralize static charges of non-conductive materials. use only the grounded tip variety of soldering iron. use proper power supply systems in testing and application. supply voltage should be applied before and removed after input signals. insertion and removal of components from sockets should be carried out with no power ap- plied. an open (floating) pin is a potential hazard to the circuit. each non connected pin should be grounded or connected to v dd through a resistor whenever possible. 4.3 firmware this part is treated by a dedicated application note (an1015) available on st website. 4.4 web links to emc related organisations fcc: federal communication commission http://www.fcc.gov eia: electronic industries alliance http://www.eia.org/ sae: society of automotive engineers http://www.sae.org iec: the international electrotechnical commission http://wwwiec.ch cenelec: european committee for electrotechnical standardisation http://ww.cenelec.be jedec: joint electron device engineering council http://www.jedec.org
37/38 emc design guide for st microcontrollers 5 conclusion for any microcontroller application, emc requirements must be considered at the very begin- ning of the development project. standards, features and parameters given in st microcon- troller datasheets will help the system designer to determine the most suitable component for a given application. hardware and firmware precautions have to be taken to optimize emc and system stability.
38/38 emc design guide for st microcontrollers the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia C belgium - brazil - canada - china C czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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